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| cortina systems ? lxt905 universal 10base-t transceiver with 3.3 v support datasheet the cortina systems ? lxt905 universal 10base-t transce iver with 3.3 v support (lxt905 transceiver) is designed for ieee 802.3 physical la yer applications. it prov ides, in a single cmos device, all the active ci rcuitry for inte rfacing most standard 802.3 controllers to 10base- t media. the lxt905 transceiver functions include the following: ? manchester encoding/decoding ? receiver squelch and transmit pulse shaping ? jabber ? link integrity testing ? reversed polarity detection/correction. the lxt905 transceiver drives the 10base-t twis ted-pair cable, with only a simple isolation transformer, using a single 3.3 v or 5 v power supply. integrated filters simplify the design work required for fcc-compliant emi performance. the lxt905 transceiver offers 10base-t connectivity solutions t hat support oper ations over an extended temperature range, while providing features that incr ease reliability. th e device has an operational lifetime of at least ten years, with less than 100 failures pe r billion hours, and is available a minimum of five years after th e introduction of the product. applications product features ? access devices (dsl, cable modems, and set-top boxes) ? routers/bridges/switches/hubs ? telecom backplane ? usb to ethernet converters ? transparent 3.3 v or 5 v operation ? integrated filters ? si mplifies fcc compliance ? integrated manchester encoder/decoder ? 10base-t compliant transceiver ? automatic polarity correction ? sqe enable/disable ? four led drivers ? full duplex capability ? power-down mode with tristate ? available in 28-pin plcc and 32-pin lqfp packages ? commercial temperature range (0 to +70oc) ? extended temperature range (-40 to +85oc)
lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 legal disclaimers this document contains information proprietary to cortina systems , inc. (cortina). any use or disclosure, in whole or in part, of this information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as authorized by cortina in writing. cortina reserves its rights to pursue both civil and criminal penalties for copying or disclo sure of this material without authorization. information in this document is prov ided in connection with cortina systems ? products. no license, express or implied, by estoppel or ot herwise, to any intellectual property rights is granted by this document. except as provided in cortina?s terms and conditi ons of sale of such products, cortina assumes no liability whatsoever, and cortina disclaims any express or implied warranty relating to the sale and/or use of cortina products, including li ability or warranties relating to fitness for a particular purpose, merchantability or infringement of any patent, copyright or other intellectual property right. cortina products are not intended for use in medical, life saving, li fe sustaining, critical control or safety systems, or in n uclear facility applications. cortina systems ? and the cortina systems logo are the trademarks or registered trademarks of cortina systems, inc. and its subsidiaries in the u.s. and other countries. other names and brands may be claimed as the property of others. copyright ? 2001 ? 2007 cortina systems, inc. all rights reserved. page 2 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support page 3 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 contents contents 1.0 pin assignments and signal descriptions ................................................................................. 7 2.0 functional description...................................................................................................... ............ 9 2.1 introduction ................................................................................................................ ........... 9 2.2 controller compatibility modes ............................................................................................. 9 2.3 transmit function ........................................................................................................... .... 10 2.4 jabber control function ..................................................................................................... 10 2.5 sqe function ................................................................................................................ ..... 11 2.6 receive function ............................................................................................................ .... 12 2.7 polarity reverse function................................................................................................... 12 2.8 collision detection function ............................................................................................... 1 3 2.9 loopback functions.......................................................................................................... .. 14 2.9.1 internal loopback .................................................................................................. 14 2.9.2 external loopback/full duplex .............................................................................. 14 2.10 link integrity test function....................... ........................................................................ .. 14 3.0 application information ..................................................................................................... ......... 16 3.1 introduction ................................................................................................................ ......... 16 3.1.1 termination circuitry..............................................................................................16 3.1.2 twisted-pair interface ............................................................................................ 16 3.1.3 rbias pin .............................................................................................................. 16 3.1.4 crystal information................................................................................................. 16 3.1.5 magnetic informat ion ............................................................................................. 17 3.2 typical 10base-t application. .............. ................ ................ ................ ................ ............. 17 3.3 dual network support - 10 base-t and token ring ... ................ ................. ............ .......... 18 3.4 simple 10base-t connection.. ................ ................ ................ ................ ................ .......... 20 4.0 test specifications ......................................................................................................... ............. 21 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) ....................................................24 4.2 timing diagrams for mode 2 (md1 = low, md0 = high)....................................................27 4.3 timing diagrams for mode 3 (md1 = high, md 0 = low)....................................................29 4.4 timing diagrams for mode 4 (md1 = high, md 0 = high) ................................................... 31 5.0 mechanical specifications ................................................................................................... ....... 33 figures 1 lxt905 transceiver block diagra m .............................................................................................. ..6 2 lxt905 pin assignments ........................................................................................................ ........ 7 3 lxt905 transceiver tpo output waveform................................................................................... 9 4 jabber control function ....................................................................................................... ......... 11 5 sqe function .................................................................................................................. .............. 12 6 collision detection function .................................................................................................. ........ 13 7 link integrity test function .......................... ........................................................................ .........15 8 intel* controller application (mode 2) ........................................................................................ .... 18 9 lxt905 transceiver/380c26 in terface for dual 10base-t and to ken ring suppor t .. (mode 4)19 10 lxt905 transceiver/mc68en360 interface for full duplex 10base-t (mode 1) ....................................................................................................................... ........... 20 11 mode 1 rclk/start-of-frame timing.................. .......................................................................... 24 page 4 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 tables 12 mode 1 rclk/end-of-frame timing ............................................................................................. 2 5 13 mode 1 transmit timing ....................................................................................................... ......... 25 14 mode 1 col output timing..................................................................................................... ......26 15 mode 2 rclk/start-of-frame........................... ........................................................................ ..... 27 16 mode 2 rclk/end-of-frame timing ............................................................................................. 2 7 17 mode 2 transmit timing ....................................................................................................... ......... 28 18 mode 2 col output timing..................................................................................................... ......28 19 mode 3 rclk/start-of-frame timing.................. .......................................................................... 29 20 mode 3 rclk/end-of-frame timing ............................................................................................. 2 9 21 mode 3 transmit timing ....................................................................................................... ......... 30 22 mode 3 col output timing..................................................................................................... ......30 23 mode 4 rclk/start-of-frame timing.................. .......................................................................... 31 24 mode 4 rclk/end-of-frame timing ............................................................................................ 3 1 25 mode 4 transmit timing ....................................................................................................... ......... 32 26 mode 4 col output timing..................................................................................................... ......32 27 lxt905pc package specifications.............................................................................................. .33 28 lxt905lc package specifications .............................................................................................. .34 tables 1 lxt905 transceiver signal descriptions ............ ............................................................................ 7 2 controller compatibility mode options ......................................................................................... .10 3 loopback modes ................................................................................................................ ........... 14 4 suitable crystals............................................................................................................. ............... 16 5 absolute maximum values ....................................................................................................... ..... 21 6 recommended operating conditions ........................................................................................... 21 7 i/o electrical characteristics ................................................................................................ ......... 21 8 tp electrical characteristics................................................................................................. ......... 22 9 switching characteristics ..................................................................................................... ......... 22 10 rclk/start-of-frame timing ............................ ....................................................................... ...... 22 11 rclk/end-of-frame timing ..................................................................................................... ..... 23 12 transmit timing .............................................................................................................. ............... 23 13 miscellaneous timing ......................................................................................................... ........... 23 page 5 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 revision history revision history revision 5.1 revision date: 5 november 2007 removed ordering and marking information. th is information is now available from www.cortina-systems.com . revision 5.0 revision date: 27 july 2007 ? first release of this document from cortina systems, inc. revision 004 revision date: 19 october 2005 ? added section 6.0, ?top-label device marking? and figure 29 through figure 32. ? modified table 16 ?product informati on? and figure 33 ?ordering information - sample? with rohs information. revision 003 revision date: 6 february 2004 ? modified table 16 ?product information? under section 6.0, ?ordering information? (replaced mm numbers). revision 002 revision date: june 2001 ? new information under ?applications?. ? added new carrier class information (paragraphs 3 and 4). ? added +5v to line status, figure 8. ? added +5v to line status, figure 9. ? added second paragraph under test specifications ?note? regarding quality and reliability issues. ? deleted ambient operating te mperatures from table 5. ? added new diagram and table for lxt 905pc/pe mechanical specifications. revision 001 revision date: october 2000 ? change resistor values for figures 7, 8, and 9. page 6 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 figure 1 lxt905 transceiver block diagram mode select logic controller compatibility / loopback / link test manchester encoder squelch/ link detect manchester decoder watch-dog timer loopback control pulse shaper & filter collision/ polarity detect/ correct cmo s tx collision logic rx slicer xtal osc rc rc li tclk clki clko ten cd ledl rclk rxd col txd md0 md1 tpop tpon tpip tpin lbk dsqe ledc/fde ledt/pdn ledr d page 7 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 1.0 pin assignments and signal descriptions 1.0 pin assignments an d signal descriptions figure 2 lxt905 pin assignments table 1 lxt905 transceiver signal descriptions (sheet 1 of 2) lqfp pin # plcc pin # symbol i/o description 13 20 27 28 29 1 22 ? ? ? vcc1 vcc2 vcc3 vcc4 vcc5 ? ? ? ? ? power inputs 1 thru 5. power supply inputs of 3.3 v or 5 v. 30 31 2 3 clki clko i o crystal oscillator. connect a 20 mhz crystal across these pins, or apply a 20 mhz clock at clki, with clko left open. 11 12 21 32 15 23 4 ? gnd1 gnd2 gnd3 gnd4 ? ? ? ? ground. 15 lbki loopback. when high, forces internal l oopback. disables collision and the transmission of both data and link pulses. pulled low internally. 1 26 teni transmit enable. enables data transmission and starts the watch-dog timer (wdt). synchronous to tclk . pulled low internally. 1 37 tclko transmit clock. a 10 mhz clock output. connect this clock signal directly to the transmit clock input of the controller. 48 txdi transmit data. input signal containing nrz data to transmit on the network. connect txd directly to the transmit data output of the controller. pulled low internally. 1 59 colo collision signal. output that drives the collision detect input of the controller. 1. externally pull-up or pull-down each pin separately using a 10 k , 1% termination resistor, or tie directly to v cc or ground. 2. do not allow this pin to float. if unused, tie high. lbk ten tclk txd col ledc/fde ledt/pdn 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 md0 tpon gnd2 vcc2 tpop dsqe rbias gnd3 clko clki vcc1 tpin tpip md1 ledr ledl cd gnd1 rclk rxd li lbk ten tclk txd col ledc/fde ledt/pdn ledr 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 ledl cd gnd1 gnd2 vcc1 rclk rxd li 9 10 11 12 13 14 15 16 md1 md0 tpon gnd3 vcc2 tpop dsqe rbias 24 23 22 21 20 19 18 17 gnd4 clko clki vcc5 vcc4 vcc3 tpin tpip lqfp plcc page 8 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 1.0 pin assignments and signal descriptions 610 ledc/ fde o i led collision or full duplex enable. ledc is an open drain driver for the col lision indicator, and pulls low during collision. extends led ?on? (which is low output) time by approximately 100 ms. fde enables full duplex mode (external l oopback) if tied low externally. pulled high internally 1 . 711 ledt/ pdn o i led transmit or power down. ledt is an open drain driver for the transmit indicator. extends led ?on? (which is low output) time by approximately 100 ms. pulls output low during transmit 2 . if externally tied low, the lxt905 goes to power down state ( pdn ). in power- down mode, ledt trislates all logic inputs and outputs. 812ledro led receive. open drain driver for the rece ive indicator led. extends led ?on? (which is low output) time by approximately 100 ms. pulls output low during receive. pulled high internally 1 . 913 ledlo led link. open drain driver for link integr ity indicator. pulls output low during link test pass. pulled high internally 1 . 10 14 cd o carrier detect. an output for notifying the contro ller that activity exists on the network. 14 16 rclk o receive clock. a recovered 10 mhz clock that is synchronous to the received data and connects to the controller receive clock input. 15 17 rxd o receive data. output signal connected directly to the receive data input of the controller. 16 18 li i link enable. controls link integrity test ? enabled when li is high ? disabled when li is low 17 19 rbias i bias circuitry. a 7.5 kw 1% resistor to ground at this pin controls operating circuit bias. 18 20 dsqe i sqe disable. ? when dsqe is high, the sqe function is disabled. ? when dsqe is low, the sqe function is enabled. disable sqe for normal operation in h ub/switch/repeater applications. pulled low internally 1 . 19 22 21 24 tpop tpon o o twisted-pair outputs. differential outputs to the twisted-pair cable. the outputs are pre-equalized. 23 24 25 26 mdo mdi i i mode select 0 and 1. mode select pins determine controller compatibility mode in accordance with table 2 . pulled low internally 1 . 25 26 27 28 tpip tpin i i twisted-pair inputs. a differential input pair from the twisted-pair cable. receive filter is integrated on-chip. does not require external filters. table 1 lxt905 transceiver signal descriptions (sheet 2 of 2) lqfp pin # plcc pin # symbol i/o description 1. externally pull-up or pull-down each pin separately using a 10 k , 1% termination resistor, or tie directly to v cc or ground. 2. do not allow this pin to float. if unused, tie high. page 9 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 2.0 functional description 2.0 functional description 2.1 introduction the lxt905 transceiver performs the physical layer signaling (pls) and media attachment unit (mau) functions, as defined in the ieee 802.3 specif ication. it functions as an integrated pls/mau for use with 10base-t twisted-pair networks. the lxt905 transceiver interfaces a back-end co ntroller to a twisted-pair (tp) cable. the controller interface includes a transmit an d receive clock and nrz data channels, and mode control logic and signaling. the twisted-pair interface comprises the following two circuits: ? twisted-pair input (tpi) ? twisted-pair output (tpo) in addition to the two basic interfaces, the lxt905 transceiver contains an internal crystal oscillator and four le d drivers for visual status reporting. the back-end controller side of the interface defines functions. ? the lxt905 transceiver transmit function refers to data transmitted by the back-end to the twisted-pair network. ? the lxt905 transceiver receive function refe rs to data received by the back-end of the twisted-pair network. the lxt905 transceiver performs all required functions defined in the ieee 802.3 10base-t mau specification as follows: ? collision detection ? link integrity testing ? signal quality error messaging ? jabber control ? loopback 2.2 controller compatibility modes the lxt905 transceiver is compatible with mo st industry standard controllers, including devices from advanced micro devices* (amd), fujitsu*, national semiconductor*, seeq*, motorola* and texas instruments*. four different control signal timing and polarity figure 3 lxt905 transceiver tpo output waveform page 10 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 2.3 transmit function schemes (modes 1 through 4) pr ovide this compatibility. th e md0 and md1 mode select pins determine controller compatibility modes (see ta b l e 2 ). refer to section 4.0, test specifications, on page 21 for timing diagrams and parameters. 2.3 transmit function the lxt905 transceiver receives nrz data from the controller at the txd input, as shown in figure 1, lxt905 transceiver block diagram, on page 6 , and passes it through a manchester encoder. the lxt905 transceiver then transfers encoded data to the twisted-pair network (tpo circuit). the ad vanced integrated pulse shaping and filtering network produces the output signal on tpon and tpop, shown in figure 3, lxt905 transceiver tpo output waveform, on page 9 . the tpo output is pre-distorted and pre- filtered to meet the 10base-t jitter template. an internal, continuous resistor-capacitor filter removes any high-frequency clocking noise from the pulse shaping circuitry. integrated filters simplify the design work required for fcc compliant emi performance. during idle periods, the lxt905 transceiver tr ansmits link integrity te st pulses on the tpo circuit (if li is enabled and lbk is disabled). 2.4 jabber control function figure 4 is a state diagram of the lxt905 transceiver jabber control function. the lxt905 transceiver on-chip watch-dog timer (wdt) prevents the dte from locking into a continuous transmit mode. when a trans mission exceeds the time limit, the wdt disables the transmit and loopback functions and activates the col pin. once the lxt905 transceiver is in the jabber state, the txd circuit must remain idle for a period of 0.25 to 0.75 seconds before it exits the jabber state. table 2 controller comp atibility mode options controller mode md1 md0 mode 1 - for motorola* mc68en360 or compatible controllers (amd* am7990) low low mode 2 - for intel* 82596 or compatible controllers low high mode 3 - for fujitsu* mb86950, mb86960 or compatible controllers (seeq* 8005) 1 high low mode 4 - for ti* tms380c26 or compatible controllers high high 1. seeq* controllers require inverters on clki, lbk, rclk and col. page 11 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 2.5 sqe function 2.5 sqe function the lxt905 transceiver supports the sig nal quality error (sqe) function (see figure 5 ) . after every successful transm ission on the 10base-t networ k, the lxt905 transceiver transmits the sqe signal for 10 bit times (b t) 5bt on the col pin of the device. ? to disable the sqe function for repeat er/switch applications, set dsqe high. ? to enable the sqe function, set dsqe low. figure 4 jabber control function no output nonjabber output start_xmit_max_timer power on do=active jab xmit=disable lpbk=disable ci=sqe unjab wait start_unjab_timer xmit=disable lpbk=disable ci=sqe do=active ? xmit_max_timer_done do=idle do=idle unjab_ timer_done do=active ? unjab_timer_not_done page 12 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 2.6 receive function 2.6 receive function the lxt905 transceiver receive function acquires timing and data from the twisted-pair network (tpi circuit). the lxt905 transceive r passes valid received signals through the on-chip filters and manchester decoder, then outputs them as decoded nrz data on the rxd pin, and as receive timing on the rclk pin. an internal rc filter and an intelligent squelch function disc riminate noise from link test pulses and valid data streams. the receive function activates only when receiving valid data streams above the squelch level with proper timing. if the differential signal at the tpi circuit inputs falls below 85 percent of the threshold level (unsquelched) for 8 bit times (typical), the lx t905 transceiver receive function enters the idle state. the lxt905 transceiver automatically corrects reversed polarity on the tpi circuit. 2.7 polarity reverse function the lxt905 transceiver polarity reverse func tion uses both link pulses and end-of-frame data to determine the polarity of the received signal. ? if you disable link integrity testing, polarit y detection is based only on received data. a reversed polarity condition exits if the lxt905 transceiver detects eight consecutive opposite receive link pulses , without receiving a link pulse of the expected polarity. figure 5 sqe function xmit=disable sqe_test_timer_done dsqe=1 do=active output idle output detected power on sqe wait test start_sqe_test__wait_timer sqe test start_sqe_test_timer ci=sqe sqe_test__wait_timer_done ? xmit=enable do=idle ? dsqe=0 page 13 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 2.8 collision detection function ? reversed polarity also occurs if the lxt905 transceiver receives four consecutive frames with a reversed start-of-idle. ? whenever the lxt905 transceiver receives a correct polarity frame or a correct link pulse, it resets these two counters to zero. ? if the lxt905 transceiver enters the link fail state, and does not receive any valid data or link pulses within 96 to 128 ms, it resets the polarity to the default non-flipped condition. polarity correction is always enabled. 2.8 collision detection function a collision is the simultaneous presence of valid signals on both the tpi ci rcuit and the tpo circuit. the lxt905 transceiver reports collis ions to the back-end via the col pin. if the tpi circuit becomes active while there is activity on the tpo circuit, the tpi data passes to the back-end over the rx d circuit, disabling normal loopback. figure 6 is a state diagram of the lxt905 transceiver collision detection function. figure 6 collision detection function idle power on a collision tpo=txd rxd=tpi col=active output tpo=txd rxd=txd input rxd=tpi ten=active ? tpi=idle ? xmit=enable ten=active ? tpi=active ? xmit=enable a a ten=active ? tpi=active ? xmit=enable ten=active ? tpi=idle ten=idle + xmit=disable ten=idle tpi=idle tpi=active page 14 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 2.9 loopback functions 2.9 loopback functions 2.9.1 internal loopback the lxt905 transceiver provid es a standard loop back mode, as specified in the ieee specification for the twisted-pair port. it al so provides a forced internal loopback mode. loopback mode operates in conjunction with the transmit function. the lxt905 transceiver internally loops back data that the mac transmits, from the txd pin, through the manchester encoder/decoder, to the rxd pin, and returning to the mac. a data collision disables standard loopback mode, clearing the rxd circuit for the tpi data. link fail, jabber, and full-duplex states also disable standard loopback. loopback is always enabled during forced internal loopback mode. 2.9.2 external loopback/full duplex the lxt905 transceiver also provides an external loopback test mode for system-level testing. when both ledc/fde and lbk are low, the lxt905 transceiver enables external loopback and full-duplex mode, and disables internal loopback circuits, sqe, and collision detection. refer to ta b l e 3 for a summary of loopback and duplex modes. 2.10 link integrity test function figure 7 is a state diagram of the lxt905 transceiver link integrity test function. the link integrity test determines the status of the re ceive side twisted-pair cable. link integrity testing is enabled when li is tied high. when enabled, the receiver recognizes link integrity pulses that transmit in the absence of receive traffic. if the lxt905 transceiver does not detect any serial data stream or lin k integrity pulses within 50~150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. the lxt905 transceiver ignores any link integrity pulse with interval less than 2~7 ms. the lxt905 remains in the link fail state until it detects either a serial data packet, or two or more link integrity pulses. table 3 loopback modes pin settings mode description lbk ledc/ fde low low disable internal loopback. enable external loopback test mode and full-duplex mode. low high standard loopback mode (default). internally loops back data that the mac transmitted, and returns the data to the mac, except during collision. a data collision disables st andard loopback, clearing rxd for data on the twisted-pair port. high low not used. high high forced internal loopback. loops-back transmit data on the receive data bus, and ignores the twisted-pair port. page 15 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 2.10 link integrity test function figure 7 link integrity test function idle test start_link_loss_timer start_link_test_min_timer power on link test fail reset link_count=0 xmit=disable rcvr=disable lpbk=disable link_loss_timer_done ? tpi=idle ? link_test_rcvd=false tpi=active + (link_test_rcvd=true ? link_test_min_timer_done) link test fail wait xmit=disable rcvr=disable lpbk=disable link_count=link_count + 1 link test fail start_link_test_min_timer start_link_test_max_timer xmit=disable rcvr=disable lpbk=disable link_test_rcvd=false ? tpi=idle tpi=active tpi=active link_test_rcvd=idle ? tpi=idle link test fail extended xmit=disable rcvr=disable lpbk=disable tpi=active + link_count=lc_max link_test_min_timer_done ? link_test_rcvd=true (tpi=idle ? link_test_max_timer_done) + (link_test_min_timer_not_done ? link_test_rcvd=true) tpi=idle ? do=idle page 16 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 3.0 application information 3.0 application information 3.1 introduction figure 8, intel* controller application (mode 2), on page 18 through figure 10, lxt905 transceiver/mc68en360 interface for full duplex 10base-t (mode 1), on page 20 show typical lxt905 transceiver applications. thes e diagrams group similar pins; they do not portray the actual chip pinout. the contro ller interface pins [transmit data (txd), transmit clock (tclk) transmit enable (t en), receive data (rxd), receive clock (rclk), collision signal (col), and carrier de tect (cd)] are at the upper left of the diagram. power and ground pins are at the bottom of each diagram. v cc 1 and v cc 2 use a single power supply, with decoupling capacitors installed between the power and ground buses. either a 5 v or 3.3 v supply can power v cc . 3.1.1 termination circuitry the lxt905 transceiver pulls several i/o pins up or down internally, to keep the signals from floating. it is recommended to hard-wire th ese pins either high or low. externally pull-up pins (ledt/pdn , ledc/fde, ledr, ledl) and pull-down pins (lbk, ten, txd, dsqe, mdo, mdi) separately, using a 10 k 1% resistor, or tie them directly to v cc or ground. 3.1.2 twisted-p air interface the twisted-pair interface (tpo p/n and tpip/n) is at the upper right of the diagram. the i/o pairs have impedance-matching resistors for 100 utp, but do not require any external filters. 3.1.3 rbias pin the rbias pin sets the levels for the lxt9 05 transceiver output drivers. the lxt905 transceiver requires a 7.5 k 1% resistor directly connec ted between the rbias pin and ground. locate this resistor as close to the de vice as possible. keep the traces as short as possible, isolated from all other high-speed signals. 3.1.4 crystal information ta b l e 4 lists some suitable crystals based on limited evaluation. test and validate all crystals before committing to a specific component. table 4 suitable crystals manufacturer part number mtron* mp-1 mp-2 page 17 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 3.2 typical 10base-t application 3.1.5 magnetic information the lxt905 transceiver requires a 1:1 turns ratio for the receive transformer, and a 1:2 turns ratio for the transmit transformer. the magnetic manufacturers for networking product applications application note (doc ument number 248991) lists transformers suitable for the applications described in this datasheet. note: test and validate all magnetics before committing to a specific component. 3.2 typical 10base-t application figure 8 is a typical lxt905 transceiver application. the dte connects to a 10base-t network through the twisted-pair rj-45 c onnector. with md0 tied high and md1 grounded, this example sets the lxt905 transceiver logic and framing to mode 2 (compatible with intel* 82596 controllers). connect 20 mhz system clock input at clki (leave clko open). the li pin externa lly controls the link test function note: refer to the cortina systems ? mac interface design guide for intel* controllers application note (document number 249007) when designing with intel* controllers. page 18 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 3.3 dual network support - 10base-t and token ring . 3.3 dual network support - 10base-t and token ring figure 9 shows the lxt905 transceiver with a texas instruments* 380c26 commprocessor. the 380c26 is compatible with mode 4 (md0 and md1 both high). when you use the lxt905 transceiver with the 380c26, you can tie both the lxt905 transceiver and a tms38054* token ring transceiver to a single rj-45, allowing dual network support from a single connector. figure 8 intel* controller application (mode 2) clko clki txd ten tclk rclk rxd cd col md0 md1 dsqe li lbk ledl ledc/fde ledt/pdn vcc1 vcc2 100 pf 50 1% not connected power down full duplex +5v 10k 10k 10k line status gnd1 gnd2 rbias programming options link test enable loopback enable 82596 back-end/ controller interface 20 mhz system clock clk txd rts txc rxc rxd crs cdt lxt905 50 1% 11.8 1% 11.8 1% 0.1 f 100 pf rj-45 tpin tpip tpon tpop 6 5 4 3 2 1 1 3 16 14 11 9 6 8 1:2 1:1 to 10 base-t twisted-pair network 7.5 k 1% 1 1 optional: center tap capacitor may improve emc depending on board layout and system design. 0.1 f page 19 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 3.3 dual network support - 10base-t and token ring figure 9 lxt905 transceiver/380c26 interface for dual 10base-t and token ring support (mode 4) txd ten tclk rclk rxd cd col lbk md0 md1 li ledr ledc/fde ledt/pdn ledl vcc1 vcc2 100 pf 50 1% +5v line status gnd2 gnd3 rbias to ti tms38054 token ring transceiver lxt905 50 1% 11.8 1% 11.8 1% 0.1 f 100 pf rj-45 tpin tpip tpon tpop 6 5 4 3 2 1 1 3 16 14 11 9 6 8 1:2 1:1 to 10 base-t twisted-pair network 7.5 k 1% 20 pf 20 mhz clki clko 1 20 pf txd txe txc rxc rxd crs col lbk 380c26 gnd1 300 300 300 300 green red red red from ti tms38054 token ring transceiver additional magnetics and switching logic (not shown) are required to implement the dual network solution. 2 optional: center tap capacitor may improve emc depending on board layout and system design. 2 1 +5v 0.1 f page 20 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 3.4 simple 10base-t connection 3.4 simple 10base-t connection figure 10 shows a simple 10base-t ap plication, using an lx t905 transceiver and a motorola* mc68en360. the mc68en360 is co mpatible with mode 1 (md0 and md1 both low). figure 10 lxt905 transceiver/mc68en360 interface for full duplex 10base-t (mode 1) rclk tclk txd rxd ten cd col lbk dsqe ledc/fde md0 md1 ledl vcc1 vcc2 li 100 pf 1 +5v gnd2 gnd3 rbias lxt905 100 11.8 1% 11.8 1% not connected 100 pf rj-45 tpin tpip tpon tpop 6 5 4 3 2 1 1 3 16 14 11 9 6 8 1:2 1:1 to 10 base-t twisted-pair network 7.5 k 1% ledc/fde requires an open-collector driver. clki clko clk1-4 clk1-4 txd rxd rts cd cts scc1 0.1 f gnd1 300 green mc68en360 20 mhz system clock 10 k parallel i/o +5v +5v 1 page 21 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.0 test specifications 4.0 test specifications note: the minimum and maximum values in ta b l e 5 through table 13 and figure 11 through figure 26 represent the performance specifications of the lxt905 transceiver. these specifications are guaranteed by test, e xcept where noted by design. minimum and maximum values in ta b l e 7 through ta b l e 1 3 apply over the recommended operating conditions specified in ta b l e 6 . table 5 absolute maximum values parameter symbol min max units supply voltage v cc -0.3 +6 v storage temperature t st -65 +150 oc caution: exceeding these values may cause permanent damage. func tional operation under these c onditions is not implied. exposure to maximum rating conditions for ex tended periods may affect device reliability. table 6 recommended operating conditions parameter symbol min typ max units recommended supply voltage 1 v cc 3.135 5.0 5.25 v recommended operating temperature (commercial) t op 0?+70oc recommended operating temperature (extended) t op -40 ? +85 oc 1. voltage is with respect to ground, unless specified otherwise. table 7 i/o electrical characteristics (sheet 1 of 2) parameter sym min typ 1 max units test conditions input low voltage 2 v il ??0.8v ? input high voltage 2 v ih 2.0 ? ? v ? output low voltage v ol ??0.4v i ol = 1.6 ma v ol ??10%v cc i ol < 10 a output low voltage (open drain led driver) v oll ??0.7%v cc i oll = 10 ma output high voltage v oh 2.4 ? ? v i oh = 40 a v oh 90 ? ? %v cc i oh < 10 a output rise time tclk & rclk cmos ? ? 3 15 ns c load = 20 pf ttl ? ? 2 15 ns ? output fall time tclk & rclk cmos ? ? 3 15 ns c load = 20 pf ttl ? ? 2 15 ns ? clki rise time (externally driven) ? ? ? 10 ns ? 1. typical values are at 25 c, are for design aid only, ar e not guaranteed, and are not subject to production testing. 2. limited functional tests are performed at t hese input levels. the majority of functi onal tests are performed at levels of 0 v and 3 v. this applies to all inputs except tpip and tpin. page 22 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.0 test specifications clki duty cycle (externally driven) ? ? 50/50 40/60 % ? supply current normal mode i cc ? 40 80 ma idle mode i cc ? 70 100 ma transmitting on tp power down mode i cc ?0.011 a? table 8 tp electrical characteristics parameter symbol min typ 1 max units test conditions transmit output impedance z out ?5? ? transmit timing jitter addition 2 ? ? 6.4 10 ns 0 line length for internal mau transmit timing jitter added by the mau and pls sections 2, 3 ? ? 3.5 5.5 ns after line model specified by ieee 802.3 for 10base-t internal mau receive input impedance z in ?24? k between tpip/tpin differential squelch threshold v ds 300 420 585 mv 5 mhz square wave input 1. typical values are at 25 c, are for design aid only, ar e not guaranteed, and are not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee 802.3 specifies maximum jitter additions at 0.5 ns from the encoder, and 3.5 ns from the mau. table 9 switching characteristics parameter symbol minimum typical 1 maximum units jabber timing maximum transmit time ? 20 ? 150 ms unjab time ? 250 ? 750 ms link integrity timing time link loss receive ? 50 ? 150 ms link min receive ? 2 ? 7 ms link max receive ? 50 ? 150 ms link transmit period ? 8 10 24 ms 1. typical values are at 25 c, are for design aid only, ar e not guaranteed, and are not subject to production testing. table 10 rclk/start-of-frame timing (sheet 1 of 2) parameter symbol min typ 1 max units decoder acquisition time t data ? 1300 1500 ns cd turn-on delay t cd ? 400 550 ns receive data setup from rclk mode 1 t rds 60 70 ? ns modes 2, 3, and 4 t rds 30 45 ? ns 1. typical values are at 25 c, are for design aid only, are not guaranteed, and are not subject to production testing. table 7 i/o electrical characteristics (sheet 2 of 2) parameter sym min typ 1 max units test conditions 1. typical values are at 25 c, are for design aid only, ar e not guaranteed, and are not subject to production testing. 2. limited functional tests are performed at t hese input levels. the majority of functi onal tests are performed at levels of 0 v and 3 v. this applies to all inputs except tpip and tpin. page 23 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.0 test specifications receive data hold from rclk mode 1 t rdh 10 20 ? ns modes 2, 3, and 4 t rdh 30 45 ? ns rclk shut off delay from cd assert (mode 3) tsws ? 100 ? ns table 11 rclk/end-of-frame timing parameter type sym mode 1 mode 2 mode 3 mode 4 units rclk after cd off min t rc 51?5bt rcv data through-put delay max t rd 400 375 375 375 ns cd turn-off delay 2 max t cdoff 500 475 475 475 ns receive block out after ten off 3 typical 1 t ifg 550? ?bt rclk switching delay after cd off typical 1 tswe ? ? 120 (80) ? ns 1. typical figures are at 25 c, are for design aid only, are not guaranteed, and are not subject to production testing. 2. cd turnoff delay, measured from middle of last bit: timing spec ification. the value of the last bit does not affect this valu e. 3. disables blocking of carrier de tect during full duplex operation. table 12 transmit timing parameter symbol minimum typical 1 maximum units ten setup from tclk t ehch 22 ? ? ns txd setup from tclk t dsch 22 ? ? ns ten hold after tclk t chel 5??ns txd hold after tclk t chdu 5??ns transmit start-up delay t stud ? 350 450 ns transmit through-put delay t tpd ? 338 350 ns 1. typical values are at 25 c, are for design aid only, ar e not guaranteed, and are not subject to production testing. table 13 miscellaneous timing parameter symbol minimum typical 1 maximum units col (sqe) delay after ten off 2 t sqed 0.65 ? 1.6 s col (sqe) pulse duration 2 t sqep 500 ? 1500 ns power down recovery time t pdr ?25?ms 1. typical values are at 25 c, are for design aid only, ar e not guaranteed, and are not subject to production testing. 2. when sqe is enabled (dsqe is low). table 10 rclk/start-of-frame timing (sheet 2 of 2) parameter symbol min typ 1 max units 1. typical values are at 25 c, are for design aid only, are not guaranteed, and are not subject to production testing. page 24 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) timing diagrams for mode 1 include figure 11 through figure 14 . figure 11 mode 1 rclk/start-of-frame timing 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t da ta tp ip /tpin cd rclk rxd t rds t rdh 0 1 0 0 0 1 0 1 0 page 25 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) figure 12 mode 1 rclk/end-of-frame timing figure 13 mode 1 transmit timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff tpip/tpin cd rclk rxd t rc ptm1_2 mode 1 rclk eof t chel t ehch t chdu ten tclk txd tpo t tpd t dsch t stud page 26 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) figure 14 mode 1 col output timing t sqep t sqed ten col page 27 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.2 timing diagrams for mode 2 (md1 = low, md0 = high) 4.2 timing diagrams for mode 2 (md1 = low, md0 = high) timing diagrams for mode 2 include figure 15 through figure 18 . figure 15 mode 2 rclk/start-of-frame figure 16 mode 2 rclk/end-of-frame timing note: 1. rxd changes at the rising edge of rclk. mode 2 samples the controller at the falling edge. 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t rds t rdh cd rclk rxd t da ta tpip/ tpin 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 t rd tpip/tpin cd rclk rxd 1 0 1 0 1 0 1 0 0 t cdoff ptm2_2 mode 2 rclk eof note: 1. rxd changes at the rising edge of rclk. mode 2 samples the controller at the falling edge. page 28 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.2 timing diagrams for mode 2 (md1 = low, md0 = high) figure 17 mode 2 transmit timing figure 18 mode 2 col output timing t chel t ehch t chdu ten tclk txd tpo t dsch t tpd t stud ptm2_3 mode 2 txmit note: 1. cd output is disabled for a maximum of 55 bit times after ten turns off. t sqed ten col t ifg t sqep page 29 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) timing diagrams for mode 3 include figure 19 through figure 22 . figure 19 mode 3 rclk/start-of-frame timing figure 20 mode 3 rclk/end-of-frame timing note: 1. rxd changes at the rising edge of rclk. mode 3 samples the controller at the falling edge. 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t da ta cd rclk rxd tp ip / tp in 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd t sws recovered from input data stream generated from tclk note: 1. rsd changes at the rising edge of rclk. mode 3 samples the controller at the falling edge. t rd t cdoff cd rclk rxd t swe recovered clock generated from tclk 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 tpip/tpin page 30 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) figure 21 mode 3 transmit timing figure 22 mode 3 col output timing t chel t ehch t chdu ten tclk txd tpo t stud t dsch t tpd t sqed ten col t sqep page 31 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) timing diagrams for mode 4 include figure 23 through figure 26 . figure 23 mode 4 rclk/start-of-frame timing figure 24 mode 4 rclk/end-of-frame timing note: 1. rxd changes at the falling edge of rclk. mode 4 samples the controller at the rising edge. 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t da ta crs rclk rxd tpip /tpin t rds t rdh 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 note: 1. rxd changes at the falling edge of rclk. mode 4 samples the controller at the rising edge. 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd tpip/tpin cd rclk rxd t cdoff page 32 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) figure 25 mode 4 transmit timing figure 26 mode 4 col output timing t chel t ehch t chdu ten tclk txd tpo t dsch t stud t tpd t sqep t sqed ten col page 33 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 5.0 mechanical specifications 5.0 mechanical specifications figure 27 lxt905pc package specifications plastic leaded chip carrier dim inches millimeters min max min max a 0.165 0.180 4.191 4.572 a 1 0.090 0.120 2.286 3.048 a 2 0.062 0.083 1.575 2.108 b 0.050 ? 1.270 ? c 0.026 0.032 0.660 0.813 d 0.485 0.495 12.319 12.573 d 1 0.450 0.456 11.430 11.582 f 0.013 0.021 0.330 0.533 28-pin plcc ? part number lxt905pc (commercial temperature range) ? part number lxt905pe (extended temperature range) page 34 cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 5.0 mechanical specifications figure 28 lxt905lc pa ckage specifications 32-pin lqfp ? part number lxt905lc (commercial temperature range) ? part number LXT905LE (extended temperature range) quad flat package dim. all dimensions in millimeters min. typ. max. notes a --- --- 1.60 a 1 0.05 0.10 0.15 a 2 1.35 1.40 1.4 d 9.00 bsc. 5 d 1 7.00 bsc. 6, 7, 8 e 9.00 bsc 5 e 1 7.00 bsc 6, 7, 8 l 0.45 0.60 0.75 m 0.15 --- --- b 0.30 0.37 0.45 9 e 0.80 bsc. notes: 1. all dimensions ar e in millimeters. 2. this package conforms to jedec publication 95 registration mo-136, variation bc. 3. datum plane -h- located at mold parting line and is coincident with leads where leads exit plastic body at bottom of parting line. 4. measured at seating plane -c-. 5. measured at datum plane -h-. 6. dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254 mm. 7. package top dimensions are smaller than bottom dimensions. top of pack age will not overhang bottom of package. 8. dimension b does not include dambar protrusion. allowable dambar protrusion is no more than 0.08 mm. e / 2 e d d 1 e e 1 all dimensions in millimeters a 1 a 2 a 0 - 7 0.08/0.20 r. o b m 11/13 8 places o 0 min. o l 1.00 ref. 0.20 min. 0.08 r. min. - h - - c - page 35 ~ end of document ~ cortina systems ? lxt905 universal 10base-t tran sceiver with 3.3 v support lxt905 transceiver datasheet 249271, revision 5.1 5 november 2007 contact information contact information cortina systems, inc. 840 w. california ave sunnyvale, ca 94086 408-481-2300 sales@cortina-systems.com apps@cortina-systems.com www.cortina-systems.com for additional product an d ordering information: www.cortina-systems.com to provide comments on this document: documentation@cortina-systems.com |
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